CY2XP304
Document #: 38-07589 Rev. *B
Page 6 of 11
DC Specifications (VCC = 3.3 V ± 5%, Commercial and Industrial temp.)
Parameter
Description
Condition
Min.
Max.
Unit
Clock Input Pair INA, INAB (HSTL differential signals)
VDIF
HSTL Differential Input Voltage[2]
0.4
1.9
V
VX
HSTL Differential Crosspoint
Voltage[3]
0.68
0.9
V
IIN
Input Current
VIN = VX ± 0.2V
|150|
uA
PECL Outputs CLK[0:3], CLK[0:3]B (PECL differential signals)
VOL
Output Low Voltage
VCC = 3.3V ± 5%
IOL = –5 mA[4]
VCC – 1.995
VCC – 1.5
V
VOH
Output High Voltage
IOH = –30 mA[4]
VCC – 1.25
VCC – 0.7
V
Supply Current and VBB
IEE
Maximum Quiescent Supply Current
without Output Termination Current
150
mA
CIN
Input Pin Capacitance
INA, INAB
3
pF
LIN
Pin Inductance
1nH
AC Electrical Specifications–Input
Parameter
Description
Min.
Max.
Unit
fIN
Input frequency with driven reference, crystal inputs
1
133
MHz
fXTAL,IN
Input frequency with crystal input
10
31.25
MHz
fINA_IN
Input Frequency with INA/INAB inputs
0
1500
MHz
CIN,CMOS
Input capacitance at PLL_MULT pin[5]
–10
pF
AC Specifications–PECL Clock Outputs CLK[0:3], CLK[0:3]B
Parameter
Description
Conditions
Min.
Max.
Unit
fO
Output Frequency
CLK_SEL = 0
125
500
MHz
CLK_SEL = 1
0
1500
MHz
Vo(P-P)
Differential output voltage
(peak-to-peak)
fO < 1GHz
0.375
–
V
VCMRO
Output Common Voltage Range
VCC – 1.425
V
tsk(O)
Output-to-output skew
400-MHz 50% duty cycle Standard load
Differential Operation
–50
ps
tsk(PP)
Part-to-part output skew
400-MHz 50% duty cycle Standard load
Differential Operation
–150
ps
TR,TF
Output Rise / Fall time
400-MHz 50% duty cycle Differential 20%
to 80%
–0.3
ns
DC
Long-term average output duty
cycle
45
55
%
tDC,ERR
Cycle-cycle duty cycle error at x8
with 15.625-MHz input
–70
ps
Phase
Noise
Phase Noise at 10 kHz (x8
mode) @ 125 MHz
–107
–92
dBc
BWLOOP
PLL Loop Bandwidth
50
kHz (–3 dB)
Notes:
2. VDIF (DC) is the amplitude of the differential HSTL input voltage swing required for device functionality.
3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operations is obtained when the crosspoint is within the VX (DC) range and the input
swing lies within the VDIF (DC) specification.
4. Equivalent to a termination of 50
Ω to VTT.
5. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.
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