Integrated Circuit Solution Inc.

1

SR020-0C

IS62LV12816L

IS62LV12816LL

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

DESCRIPTION

The

2.097,152-bit static RAMs organized as 131,072 words by 16

bits. They are fabricated using

technology. This highly reliable process coupled with innova-

tive circuit design techniques, yields high-performance and

low power consumption devices.

When CE is HIGH (deselected) or when CE is low and both LB

and UB are HIGH, the device assumes a standby mode at

which the power dissipation can be reduced by using CMOS

input levels.

Easy memory expansion is provided by using Chip Enable

Output and Enable inputs, CE and OE. The active LOW Write

Enable (WE) controls both writing and reading of the memory.

A data byte allows Upper Byte (UB) and Lower Byte (LB)

access.

The IS62LV12816L and IS62LV12816LL are packaged in the

JEDEC standare 44-pin 400mil TSOP-2 and 48-pin 6*8mm

TF-BGA.

FUNCTIONAL BLOCK DIAGRAM

A0-A16

CE

OE

WE

128K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB

IS62LV12816L

IS62LV12816LL

128K x 16 LOW VOLTAGE, ULTRA

LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access times: 55, 70, 100 ns

• CMOS low power operation

-- 120 mW (typical) operating

-- 6 µW (typical) CMOS standby

• TTL compatible interface levels

• Single 2.7V-3.6V Vcc power supply

• Fully static operation: no clock or refresh re-

quired

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in the 44-pin TSOP-2 and 48-pin

6*8mm TF-BGA