IC89C52(51)A

Integrated CircuitSolution Inc.

9

MC008-0C 11/27/2001

Program Verify

If lock bits LB2 and LB3 have not been programmed,

the programmed code data can be read back via the ad-

dress and data lines for verification. ‘C0H’ command is

needed for switching to program verify mode. During pro-

gram verify, the code memory use the internally-gener-

ated higher margin voltage to the addressed byte.

Normal Verify

If lock bits LB2 and LB3 have not been programmed,

the programmed code data can be read back via the ad-

dress and data lines for verification. If flash command

decoder receives the ‘00H’ command or IC89C52(51)A

power is initialized, the command decoder switches to

normal verify mode. During normal verify, the code

memory use the same threshold as instruction executing

threshold.

Erase Verify

If lock bits LB2 and LB3 have not been programmed,

the programmed code data can be read back via the ad-

dress and data lines for verification. ‘A0H’ command is

needed for switching to erase verify mode. During erase

verify, the code memory use the internally-generated lower

margin voltage to the addressed byte.

Program Lock Bit 1, 2, 3

The lock bit 1, 2, 3 is programmed by using the erase

command ‘60H’, ‘70H’ and ‘80H’ in the first cycle. In the

second cycle, the ‘D0H’ command is presented on whole

PROG strobe time. The PROG strobe time is real lock

bits programming time. The

PROG rising edge will clear

the erasing state to normal verify state. The programming

lock bits operations don’t use the smart algorithm but it is

programmed 10 times directly. If programming lock bits

are needed, it must be programmed after the encryption

array and code memory programming.

The IC89C52(51)A lock bits programming flow is

described in Figure 7.

Chip Erase

All flash cell must be programmed to ‘00’ before the

chip is erased. The programming sequence is encryption

array, code memory and lock bit 1, 2, 3. The entire flash

array is erased electrically by using the erase command

‘20H’ in the first cycle. In the second cycle, the ‘D0H’

command is presented on whole

PROG strobe time. The

PROG strobe time is real flash erasing time. The PROG

rising edge will clear the erasing state to normal verify

state. The code array is written with all “1”s. The chip erase

operation must be executed before the code memory can

be re-programmed. If the any flash cell is not ‘1’ (include

encryption array and lock bits) repeat erase condition less

than 50 times.

The IC89C52(51)A detail erase flow is described in

Figure 8.

Reading the Signature Bytes:

The signature bytes are read by the same procedure as

a normal verification of locations 030H, 031H and 032H,

except that command is ‘90H’. The values returned are:

(030H) = D5H indicates manufactured by ICSI

(031H) = 52H indicates IC89C52A/IC89C51A

(032H) = AAH indicates programming voltage is 12V

55H indicates programming voltage is 5V

The signatures can be read by following conditions. It’s

easier to recognize by programmer.

1. RST = high level.

PSEN = Low level. PROG = High

level. VPP = High Level. P2.6 = Low level. P2.7 = Low

level. P3.6 = Low level. P3.7 = Low level.

2. Address is switched to (030H), (031H) and (032H). Then

the Data bus outputs the D5H, 52H, AAH (55H).

Program Lock bits

Protection Type

LB1

LB2

LB3

1

U

U

U

No program lock feature enabled.

2

P

U

U

MOVC instructions executed from external program memory are disabled from fetching

code bytes from internal memory,

EA is sampled and latched on reset, and further

programming of the Flash is disabled.

3P

P

U

Same as 2, also verify is disabled

4P

P

P

Same as 3, also external execution is disabled

Lock bits Features