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IC89C52A-12W Datasheet(PDF) 5 Page - Integrated Circuit Solution Inc |
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IC89C52A-12W Datasheet(HTML) 5 Page - Integrated Circuit Solution Inc |
5 / 22 page IC89C52(51)A Integrated CircuitSolution Inc. 5 MC008-0C 11/27/2001 Table 1. Detailed Pin Description Symbol PDIP PLCC PQFP I/O Name and Function ALE/ PROG 30 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the Program Pulse input ( PROG) during Flash programming. EA/VPP 31 35 29 I External Access enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 1FFFH . If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 1FFFH. This also receives the 12V programming enable voltage (VPP) during Flash programming. P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high- impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting 1s. Port 0 also receives the command and code bytes during programmable memory programming and outputs the code bytes during program verification. External pullups are required during program verification. P1.0-P1.7 1-8 2-9 40-44 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal 1-3 pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). The Port 1 output buffers can sink/source four TTL inputs. Port 1 also receives the low-order address byte during Flash programming and verification. 12 40 I T2(P1.0): Timer/Counter 2 external count input.(IC89C52A only) 23 41 I T2EX(P1.1): Timer/Counter 2 trigger input.(IC89C52A only) P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). Port 2 emits the high order address byte during fetches from external pro- gram memory and during accesses to external data memory that used 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order bits and some control signals during Flash programming and verification. P2.6 and P2.7 are the control signals while the chip programs and erases. |
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