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Integrated Circuit Solution Inc.

LPSR015-0A 1/3/2001

IC62LV1008L

IC62LV1008LL

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

DESCRIPTION

The

1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using

device is targeted to satisfy the demands of the state-of-the-art

technologies such as cell phones and pagers.

When

assumes a standby mode at which the power dissipation can

be reduced down with CMOS input levels. Additionally, easy

memory expansion is provided by using two Chip Enable

inputs,

controls both writing and reading of the memory.

The IC62LV1008L and IC62LV1008LL are available in know

good die form and 48-pin 8*10mm TF-BGA.

FUNCTIONAL BLOCK DIAGRAM

CMOS STATIC RAM

FEATURES

• Access times of 55, 70, 100 ns

• CMOS Low power operation:

• Low data retention voltage: 1.5V (min.)

• Output Enable (

OE) and Two Chip Enables

(CE1, CE2) inputs for ease in applications

• TTL compatible inputs and outputs

• Fully static operation:

—

No clock or refresh reguired

• Single 2.7V-3.6V power supply

• Wafer level burn in test mode

• Available in the know good die form and

48-pin 8*10mm TF-BGA

*

Preliminary

A0-A19

CE1

OE

WE

1024K x 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

CE2