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IC62VV1008L Datasheet(PDF) 2 Page - Integrated Circuit Solution Inc |
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IC62VV1008L Datasheet(HTML) 2 Page - Integrated Circuit Solution Inc |
2 / 11 page ![]() 2 Integrated Circuit Solution Inc. LPSR026-0A 9/4/2002 IC62VV1008L IC62VV1008LL ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. DESCRIPTION The ICSI IC62VV1008L and IC62VV1008LL is a low voltage, 1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using ICSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable ( WE) controls both writing and reading of the memory. The IC62VV1008L and IC62VV1008LL are available in know good die form and 48-pin 8*10mm TF-BGA. FUNCTIONAL BLOCK DIAGRAM 1M x 8 1.8V ULTRA LOW POWER CMOS STATIC RAM FEATURES • Access times of 70, 100 ns • CMOS Low power operation: ICC=10mA (typical)* operation ISB2=3µA (typical)* standby • Low data retention voltage: 1.2V (min.) • Output Enable ( OE) and Two Chip Enables (CE1, CE2) inputs for ease in applications • TTL compatible inputs and outputs • Fully static operation: — No clock or refresh reguired • Single 1.65V-2.2V power supply • Wafer level burn in test mode • Available in the know good die form and 48-pin 8*10mm TF-BGA * Typical values are measured at VCC=1.8V, TA=25°C Preliminary A0-A19 CE1 OE WE 1024K x 8 MEMORY ARRAY DECODER COLUMN I/O CONTROL CIRCUIT GND VCC I/O DATA CIRCUIT I/O0-I/O7 CE2 |