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IC41LV16105S-50KI Datasheet(PDF) 1 Page - Integrated Circuit Solution Inc |
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IC41LV16105S-50KI Datasheet(HTML) 1 Page - Integrated Circuit Solution Inc |
1 / 18 page ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. .EATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms, 1,024 cycles / 128ms Self Refresh Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden, and Self Refresh JEDEC standard pinout Single power supply: 5V ± 10% (IC41C16105S) 3.3V ± 10% (IC41LV16105S) Byte Write and Byte Read operation via two CAS Industrail temperature range -40oC to 85oC DESCRIPTION The 1+51 IC41C16105S and IC41LV16105S are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. .ast Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IC41C16105S ideal for use in 16-, 32-bit wide data bus systems. These features make the IC41C16105S and IC41LV16105S ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IC41C16105S and IC41LV16105S are packaged in a 42-pin 400mil SOJ and 400mil 44- (50-) pin TSOP-2. IC41C16105S IC41LV16105S 1M x 16 (16-MBIT) DYNAMIC RAM WITH .AST PAGE MODE KEY TIMING PARAMETERS Parameter -50 -60 Unit Max. RAS Access Time (tRAC)50 60 ns Max. CAS Access Time (tCAC)13 15 ns Max. Column Address Access Time (tAA)25 30 ns Min. .ast Page Mode Cycle Time (tPC)20 25 ns Min. Read/Write Cycle Time (tRC) 84 104 ns 42-Pin SOJ PIN CON.IGURATIONS 44(50)-Pin TSOP-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND PIN DESCRIPTIONS A0-A9 Address Inputs I/O0-15 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vcc Power GND Ground NC No Connection 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC NC WE RAS NC NC A0 A1 A2 A3 VCC GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND Integrated Circuit Solution Inc. 1 DR011-0A 05/23/2001 |
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