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IC41SV44052-100T Datasheet(PDF) 4 Page - Integrated Circuit Solution Inc

Part # IC41SV44052-100T
Description  4Mx4 bit Dynamic RAM with Fast Page Mode
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Manufacturer  ICSI [Integrated Circuit Solution Inc]
Direct Link  http://www.icsi.com.tw
Logo ICSI - Integrated Circuit Solution Inc

IC41SV44052-100T Datasheet(HTML) 4 Page - Integrated Circuit Solution Inc

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IC41SV44052
IC41SV44054
4
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
Functional Description
The IC41SV44052 and IC41LV44054 are CMOS DRAMs
optimized for high-speed bandwidth, low power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 11 or 12 address bits. These are
entered 11 bits (A0-A10) at a time for the 2K refresh device
or 12 bits (A0-A11) at a time for the 4K refresh device. The
row address is latched by the Row Address Strobe (
RAS).
The column address is latched by the Column Address
Strobe (
CAS). RAS is used to latch the first nine bits and
CAS is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring
RAS LOW and it is
terminated by returning both
RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum tRAS time has expired. A new cycle
must not be initiated until the minimum precharge time tRP,
tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS or OE,
whichever occurs last, while holding
WE HIGH. The col-
umn address must be held for a minimum time specified by
tAR. Data Out becomes valid only when tRAC, tAA, tCAC and
tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS or WE, whichever occurs
last.
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in each
64ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) or 4096 row addresses (A0 through A11)
with RAS at least once every 32 ms or 64ms respectively.
Any read, write, read-modify-write or RAS-only cycle
refreshes the addressed row.
2. Using a
CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding
CAS LOW. In CAS-before-RAS refresh
cycle, an internal 11(12)-bit counter provides the row
addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initializa-
tion cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS track with
VCC or be held at a valid VIH to avoid current surges.


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