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IC41C1664-40T Datasheet(PDF) 5 Page - Integrated Circuit Solution Inc |
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IC41C1664-40T Datasheet(HTML) 5 Page - Integrated Circuit Solution Inc |
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5 / 21 page  IC41C1664 IC41LV1664 Integrated Circuit Solution Inc. 5 DR033-0A 11/15/2001 Functional Description The IC41C1664 and IC41LV1664 is a CMOS DRAM optimized for high-speed bandwidth, low power applica- tions. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered 8 bits (A0-A7) at a time. The row address is latched by the Row Address Strobe ( RAS). The column address is latched by the Column Address Strobe ( CAS) . The IC41C1664 and IC41LV1664 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical man- ner to the single CAS input on the other 64K x 16 DRAMs. The key difference is that each CAS controls its corre- sponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15. The IC41C1664 and IC41LV1664 CAS function is deter- mined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IC41C1664 both BYTE READ and BYTE WRITE cycle capabilities. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOE are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs first. Refresh Cycle To retain data, 256 refresh cycles are required in each 4 ms period. There are two ways to refresh the memory. 1. By clocking each of the 256 row addresses (A0 through A7) with RAS at least once every 4 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the ad- dressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 8-bit counter provides the row ad- dresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Extended Data Out Page Mode EDO page mode operation permits all 256 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write opera- tions during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case. Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initial- ization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. |
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