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IC41C4100-50J Datasheet(PDF) 10 Page - Integrated Circuit Solution Inc

Part No. IC41C4100-50J
Description  1Mx4 bit Dynamic RAM with EDO Page Mode
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Manufacturer  ICSI [Integrated Circuit Solution Inc]
Direct Link  http://www.icsi.com.tw
Logo ICSI - Integrated Circuit Solution Inc

IC41C4100-50J Datasheet(HTML) 10 Page - Integrated Circuit Solution Inc

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IC41C4100
IC41LV4100
10
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If
CAS and RAS = VIH, data output is High-Z.
5. If
CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD
≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD
≥ tRCD (MAX).
9. If
CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer,
CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS
≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD
≥ tRWD
(MIN), tAWD
≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until
CAS and RAS or OE go back
to VIH) is indeterminate.
OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding
CAS input.
16. During a READ cycle, if
OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as
WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (
OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if
CAS remains LOW
and
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first
χCAS edge to transition LOW.
21. The last
χCAS edge to transition HIGH.
22. These parameters are referenced to
CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling
χCAS edge to first rising χCAS edge.
24. Last rising
χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising
χCAS edge to first falling χCAS edge.
26. Each
χCAS must meet minimum pulse width.
27. Last
χCAS to go LOW.
28. I/Os controlled, regardless
CAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.


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