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LM3489MMX Datasheet(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # LM3489MMX
Description  Hysteretic PFET Buck Controller with Enable Pin
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM3489MMX Datasheet(HTML) 10 Page - National Semiconductor (TI)

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Functional Description (Continued)
The minimum output voltage ripple (V
OUT_PP) can be calcu-
lated in the same way.
V
OUT_PP =VHYST (R1+R2)/R2
For example, with V
OUT set to 3.3V, VOUT_PP is 26.6mV
V
OUT_PP = 0.01 x (33K + 20k) / 20k = 0.0266V
Operating frequency (F) is determined by knowing the input
voltage, output voltage, inductor, V
HYST, ESR (Equivalent
Series Resistance) of output capacitor, and the delay. It can
be approximately calculated using the formula:
where:
α:(R1+R2)/R2
delay: It includes the LM3489 propagation delay time
and
the PFET delay time. The propagation delay is 90ns
typically. (See the Propagation Delay curve below.)
The operating frequency and output ripple voltage can also
be significantly influenced by the speed up capacitor (Cff).
Cff is connected in parallel with the high side feedback
resistor, R1. The location of this capacitor is similar to where
a phase lead capacitor would be located in a PWM control
scheme. However it’s effect on hysteretic operation is much
different. Cff effectively shorts out R1 at the switching fre-
quency and applies the full output ripple to the FB pin without
dividing by the R2/R1 ratio. The end result is a reduction in
output ripple and an increase in operating frequency. When
adding Cff, calculate the formula above with
α = 1. The value
of Cff depend on the desired operating frequency and the
value of R2. A good starting point is 470pF ceramic at
100kHz decreasing linearly with increased operating fre-
quency. Also note that as the output voltage is programmed
below 2.5V, the effect of Cff will decrease significantly.
CURRENT LIMIT OPERATION
The LM3489 has a cycle-by-cycle current limit. Current limit
is sensed across the V
DS of the PFET or across an addi-
tional sense resistor. When current limit is activated, the
LM3489 turns off the external PFET for a period of 9µs(typi-
cal). The current limit is adjusted by an external resistor,
R
ADJ.
The current limit circuit is composed of the ISENSE com-
parator and the one-shot pulse generator. The positive input
of the ISENSE comparator is the ADJ pin. An internal 5.5µA
current sink creates a voltage across the external R
ADJ
resistor. This voltage is compared to the voltage across the
PFET or sense resistor. The ADJ voltage can be calculated
as follows:
V
ADJ =VIN −(RADJ x 3.0µA)
Where 3.0µA is the minimum I
CL-ADJ value.
The negative input of the ISENSE comparator is the ISENSE
pin that should be connected to the drain of the external
PFET. The inductor current is determined by sensing the
V
DS. It can be calculated as follows.
V
ISENSE =VIN −(RDSON xIIND_PEAK)=VIN −VDS
The current limit is activated when the voltage at the ADJ pin
exceeds the voltage at the I
SENSE pin. The ISENSE com-
parator triggers the 9µs one shot pulse generator forcing the
driver to turn the PFET off. The driver turns the PFET back
on after 9µs. If the current has not reduced below the set
threshold, the cycle will repeat continuously.
A filter capacitor, C
ADJ, should be placed as shown in Figure
3.C
ADJ filters unwanted noise so that the ISENSE compara-
tor will not be accidentally triggered. A value of 100pF to 1nF
is recommended in most applications. Higher values can be
used to create a soft-start function (See Start Up section).
The current limit comparator has approximately 100ns of
blanking time. This ensures that the PFET is fully on when
the current is sensed. However, under extreme conditions
such as cold temperature, some PFETs may not fully turn on
within the blanking time. In this case, the current limit thresh-
old must be increased. If the current limit function is used,
the on time must be greater than 100ns. Under low duty
cycle operation, the maximum operating frequency will be
limited by this minimum on time.
During current limit operation, the output voltage will drop
significantly as will operating frequency. As the load current
is reduced, the output will return to the programmed voltage.
However, there is a current limit fold back phenomenon
inherent in this current limit architecture. See Figure 4.
20186914
FIGURE 2. Propagation Delay
20186925
FIGURE 3. Current Sensing by V
DS
www.national.com
10


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