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W83194BR-372 Datasheet(PDF) 11 Page - Winbond |
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W83194BR-372 Datasheet(HTML) 11 Page - Winbond |
11 / 24 page W83194BR-372 Publication Release Date: April 13, 2005 - 7 - Revision 1.1 7.4 Register 3: AGP, 24_48MHz, 48MHz, REF Control (1 =Enable, 0 =Stopped) (Default: FFh) BIT PIN NO PWD DESCRIPTION 7 30 1 AGP_1 output control 6 31 1 AGP_0 output control 5 26 1 24_48MHz output control 4 27 1 48MHz output control 3 4 1 REF2 output control 2 3 1 REF1 output control 1 2 1 REF0 output control 0 - 1 Reserved 7.5 Register 4: IOAPIC, ZCLK Control (1 = Enable, 0 = Stopped) (Default: F0h) BIT PIN NO PWD DESCRIPTION 7 47 1 IOAPIC1 output control 6 46 1 IOAPIC0 output control 5 10 1 ZCLK1 output control 4 9 1 ZCLK0 output control 3 - 0 Reserved 2 SEL<2> 0 1 SEL<1> 0 0 SEL<0> 0 Asynchronous ZCLK/AGP/PCI frequency table selection, SEL<2:0> 001: 132 / 66 / 33M 010:132 / 75.43 / 37.7M 011: 132 / 88 / 44M 100:176 / 88 / 44M 101: 132 / 66 / 33M 110:132 / 75.43 / 33M 111: 132 / 88 / 33M 000: Clock from PLL1 7.6 Register 5: 24_48MHz Control (Default: 88h) BIT NAME PWD DESCRIPTION 7 SEL24_48 1 24 / 48 MHz output selection, 1: 24 MHz (Default), 0: 48 MHz. 6 Reserved 0 Reserved 5 Reserved 0 Reserved 4 Reserved 0 3 Reserved 1 2 Reserved 0 1 Reserved 0 0 Reserved 0 Reserved |
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