CY7C1371B
CY7C1373B
Document #: 38-05198 Rev. **
Page 7 of 26
three-state the output drivers. As a safety precaution, DQ and
DP are automatically three-stated during the data portion of a
Write cycle, regardless of the state of OE.
Burst Write Access
The CY7C1371B/CY7C1373B has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the chip enables (CE1, CE2, and CE3) and
WE inputs are ignored and the burst counter is incremented.
The correct BWSa,b,c,d/BWSa,b inputs must be driven in each
cycle of the burst Write in order to write the correct bytes of
data.
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Operation
Address
Used
CE
CEN
ADV/
LD
WE
BWSX
CLK
Comments
Deselected
External
1
0
0
X
X
L–H
I/Os three-state following next recog-
nized clock.
Suspend
–
X
1
XXX
L–H
Clock ignored, all operations
suspended.
Begin Read
External
0
0
0
1
X
L–H
Address latched.
Begin Write
External
0
0
0
0
Valid
L–H
Address latched, data presented two
valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L–H
Burst Read operation. Previous
access was a Read operation.
Addresses incremented internally in
conjunction with the state of MODE.
Burst Write
Operation
Internal
X
0
1
X
Valid
L–H
Burst Write operation. Previous
access was a Write operation.
Addresses incremented internally in
conjunction with the state of MODE.
Bytes written are determined by
BWSa,b,c,d/BWSa,b.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Notes:
1.
X = “Don’t Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL chip enables. CE = 0 stands for ALL chip enables active.
2.
Write is defined by WE and BWSx. BWSx = Valid signifies that the desired byte Write selects are asserted. See Write Cycle Description table for details.
3.
The DQ and DP pins are controlled by the current cycle and the OE signal.
4.
CEN = 1 inserts wait states.
5.
Device will power-up deselected and I/Os in a three-state condition, regardless of OE.
6.
OE assumed LOW.
ZZ-Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD – 0.2V
20
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
