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IDT72V73273 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT72V73273
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V73273 Datasheet(HTML) 6 Page - Integrated Device Technology

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INDUSTRIAL TEMPERATURERANGE
IDT72V73273 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS
DESCRIPTION (CONTINUED):
The IDT72V73273 is capable of switching up to 32,768 x 32,768 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delay for voice applications on a per-channel basis.
The 64 serial input streams (RX) of the IDT72V73273 can be run at
2.048Mb/s, 4.096Mb/s, 8.192Mb/s, 16.384Mb/s or 32.768Mb/s allowing 32,
64, 128, 256 or 512 channels per 125
µs frame. The data rates on the output
streams can independently be programmed to run at any of these data rates.
Withtwomainoperatingmodes,ProcessorModeandConnectionMode,the
IDT72V73273 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor via Connection Memory.
Ascontrolandstatusinformationiscriticalindatatransmission,theProcessor
Modeisespeciallyusefulwhentherearemultipledevicessharingtheinputand
outputstreams.
With data coming from multiple sources and through different paths, data
enteringthedeviceisoftendelayed.Tohandlethisproblem,theIDT72V73273
hasaFrameOffset featuretoallowindividualstreamstobeoffsetfromtheframe
pulse in half clock-cycle intervals up to +7.5 clock cycles.
The IDT72V73273 also provides a JTAG test access port, memory block
programming, Group Block Programming, RX/TX internal bypass, a simple
microprocessor interface and automatic ST-BUS/GCI sensing to shorten
setup time, aid in debugging and ease use of the device without sacrificing
capabilities.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (F32i) is used to mark the 125
µsframeboundariesandtosequentially
address the input channels in Data Memory.
Data output on the TX streams may come from either the serial input streams
(Data Memory) or from the Connection Memory via the microprocessor or in
thecasethatRXinputdataistobeoutput,theaddressesinConnectionMemory
areusedtospecifyastreamandchanneloftheinput.TheConnectionMemory
is setup in such a way that each location corresponds to an output channel for
eachparticularstream.Inthatway,morethanonechannelcanoutputthesame
data. In Processor Mode, the microprocessor writes data to the Connection
Memorylocationscorrespondingtothestreamandchannelthatistobeoutput.
Thelowerhalf(8leastsignificantbits)oftheConnectionMemoryLOW isoutput
everyframeuntilthemicroprocessorchangesthedataormodeofthechannels.
By using this Processor Mode capability, the microprocessor can access input
and output time-slots on a per-channel basis.
The three least significant bits of the Connection Memory HIGH are used to
control per-channel mode of the output streams. The MOD2-0 bits are used to
select Processor Mode, Constant or Variable Delay Mode, Bit Error Rate, and
the High-Impedance state of output drivers. If the MOD2-0 bits are set to 1-1-1
accordingly, only that particular output channel (8 bits) will be in the High-
Impedancestate.IftheMOD2-0bitsaresetto1-0-0accordingly,thatparticular
channelwillbeinProcessorMode. IftheMOD2-0bitsaresetto1-0-1aBitError
Rate Test pattern will be transmitted for that time slot. See BERT section. If the
MOD2-0 bits are set to 0-0-1 accordingly, that particular channel will be in
ConstantDelayMode.Finally,iftheMOD2-0bitsaresetto0-0-0,thatparticular
channel will be in Variable Delay Mode.
SERIAL DATA INTERFACE TIMING
The master clock frequency of the IDT72V73273 is 32.768MHz, C32i. For
32.768Mb/s data rates, this results in a single-bit per clock. For 16.384Mb/s,
8.192Mb/s, 4.096Mb/s, and 2.048Mb/s this will result in two, four, eight, and
sixteen clocks per bit, respectively. The IDT72V73273 provides two different
interface timing modes, ST-BUSor GCI. The IDT72V73273 automatically
detects the polarity of an input frame pulse and identifies it as either ST-BUS
or GCI.
For 32.768Mb/s, in ST-BUSMode, data is clocked out on a falling edge and
is clocked in on the subsequent rising-edge. For 16.384Mb/s, 8.192Mb/s,
4.096Mb/s, and 2.048Mb/s however there is not the typical associated clock
since the IDT72V73273 accepts only a 32.768MHz clock. As a result there will
be 2, 4, 8, and 16 clock between the 32.768Mb/s transmit edge and the
subsequently transmit edges. Although in this is the case, the IDT72V73273
will appropriately transmit and sample on the proper edge as if the respective
clock were present. See ST-BUSTiming for detail.
For 32.768Mb/s, in GCI Mode, data is clocked out on a rising edge and is
clocked in on the subsequent falling-edge. For 16.384Mb/s, 8.192Mb/s,
4.096Mb/s, and 2.048Mb/s however, again there is not the typical associated
clocksincetheIDT72V73273acceptsonlya32.768MHzclock. Asaresultthere
will 2, 4, 8, and 16 clocks between the 32.768Mb/s transmit edge and the other
transmit edges. Although this is the case, the IDT72V73273 will appropriately
transmitandsampleontheproperedgeasiftherespectiveclockwerepresent.
See GCI Bus Timing for detail.
DELAY THROUGH THE IDT72V73273
The switching of information from the input serial streams to the output serial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabilities
onaper-channelbasis.Forvoiceapplications,variablethroughputdelayisbest
as it ensure minimum delay between input and output data. In wideband data
applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
Thedelaythroughthedevicevariesaccordingtothetypeofthroughputdelay
selected in the MOD bits of the Connection Memory.
VARIABLE DELAY MODE (MOD2-0 = 0-0-0)
In this mode, mostly for voice applications where minimum throughput delay
is desired, delay is dependent on the combination of source and destination
channels. The minimum delay achievable is a 3 channel periods of the slower
data rate .
CONSTANT DELAY MODE (MOD2-0 = 0-0-1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
theIDT72V73273,theminimumthroughputdelayachievableinConstantDelay
mode will be one frame plus one channel. See Table 14.


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