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IDT72V73273 Datasheet(PDF) 4 Page - Integrated Device Technology

Part No. IDT72V73273
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V73273 Datasheet(HTML) 4 Page - Integrated Device Technology

 
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INDUSTRIAL TEMPERATURERANGE
IDT72V73273 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS
PIN DESCRIPTION
A0-A15
Address 0-15
I
*See PQFP
*See PBGA
These address lines access all internal memories.
Table Below
Table Below
BEL
Byte Enable LOW
I
31
L4
In synchronous mode, this input will enable the lower byte (D0-7) on to the data
bus.
C32i
Clock
I
2
A1
Serial clock for shifting data in/out on the serial data streams. This input accepts
a 32.768MHz clock.
CS
Chip Select
I
12
E1
Active LOW input used by a microprocessor to activate the microprocessor port
of the device.
D0-15
Data Bus 0-15
I/O
*See PQFP
*See PBGA
These pins are the data bus of the microprocessor port.
Table Below
Table Below
DS
DataStrobe
I
11
D4
This active LOW input works in conjunction with
CS to enable the read and write
operations. This active LOW input sets the data bus lines (D0-D15).
DTA/BEH
DataTransfer
I/O
32
K2
In asynchronous mode this pin indicates that a data bus transfer is complete.
Acknowledgment
When the bus cycle ends, this pin drives HIGH and then High-Z allowing for
Active LOW Output
faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to
/Byte Enable HIGH
hold a HIGH level when the pin is High-Z. When the device is in
synchronous bus mode, this pin acts as an input and will enable the upper byte
(D8-15) on to the data bus.
F32i
Frame Pulse
I
3
B1
This input accepts and automatically identifies frame synchronization signals
formatted according to ST-BUSand GCI specifications.
GND
*See PQFP
*See PBGA
Ground.
Table Below
Table Below
ODE
Output Drive Enable
I
207
A3
This is the output enable control for the TX serial outputs. When ODE input is
LOW and the OSB bit of the CR register is LOW, all TX outputs are in a High-
Impedance state. If this input is HIGH, the TX output drivers are enabled.
However, each channel may still be put into a High-Impedance state by using
the per channel control bits in the Connection Memory HIGH.
RX0-63
RX Input 0 to 63
I
*See PQFP
*See PBGA
Serial data Input Stream. These streams may have data rates of 2.048Mb/s,
Table Below
Table Below
4.096Mb/s, 8.192Mb/s, 16.384Mb/s, or 32.768Mb/s depending upon the
selection in Receive Data Rate Selection Register (RDRSR).
RESET
Device Reset:
I
208
A2
This input (active LOW) puts the device in its reset state that clears the device
internal counters, registers and brings TX0-63 and microport data outputs to a
High-Impedance state. The
RESET pin must be held LOW for a minimum of
20ns to reset the device.
R/
W
Read/Write
I
13
E2
This input controls the direction of the data bus lines (D0-D15) during a
microprocessor access.
S/
A
Synchronous/
I
5
C1
This input will select between asynchronous microprocessor bus timing and
Asynchronous
synchronous microprocessor bus timing. In synchronous mode,
DTA/BEH
Bus Mode
acts as the
BEH input and is used in conjunction with BEL to output data on the
data bus. In asynchronous bus mode,
BEL is tied LOW and DTA/BEH acts as
the DTA, data bus acknowledgment output.
TCK
Test Clock
I
9
D2
Provides the clock to the JTAG test logic.
TDI
Test Serial Data In
I
7
C3
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled
HIGH by an internal pull-up when not driven.
TDO
Test Serial Data Out
O
8
D1
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held i
in High-Impedance state when JTAG scan is not enabled.
TMS
Test Mode Select
I
6
C2
JTAG signal that controls the state transitions of the TAP controller. This pin is
pulled HIGH by an internal pull-up when not driven.
TRST
TestReset
I
10
D3
Asynchronously initializes the JTAG TAP controller by putting it in the Test-
Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This
pin should be pulsed LOW on power-up, or held LOW, to ensure that the device
SYMBOL
NAME
I/O
PQFP
PBGA
DESCRIPTION
PIN NO.
PIN NO.


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