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XC164S Datasheet(PDF) 62 Page - Infineon Technologies AG |
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XC164S Datasheet(HTML) 62 Page - Infineon Technologies AG |
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62 / 72 page  XC164S Derivatives Timing Parameters Data Sheet 58 V1.0, 2005-01 Bypass Operation When bypass operation is configured (PLLCTRL = 0x B) the master clock is derived from the internal oscillator (input clock signal XTAL1) through the input- and output- prescalers: f MC = fOSC / ((PLLIDIV+1)×(PLLODIV+1)). If both divider factors are selected as ’1’ (PLLIDIV = PLLODIV = ’0’) the frequency of f MC directly follows the frequency of f OSC so the high and low time of fMC is defined by the duty cycle of the input clock f OSC. The lowest master clock frequency is achieved by selecting the maximum values for both divider factors: f MC = fOSC / ((3+1)×(14+1)) = fOSC / 60. Phase Locked Loop (PLL) When PLL operation is configured (PLLCTRL = 11 B) the on-chip phase locked loop is enabled and provides the master clock. The PLL multiplies the input frequency by the factor F ( f MC = fOSC × F) which results from the input divider, the multiplication factor, and the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit synchronizes the master clock to the input clock. This synchronization is done smoothly, i.e. the master clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of f MC is constantly adjusted so it is locked to f OSC. The slight variation causes a jitter of fMC which also affects the duration of individual TCMs. The timing listed in the AC Characteristics refers to TCPs. Because f CPU is derived from f MC, the timing must be calculated using the minimum TCP possible under the respective circumstances. The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCP is lower than for one single TCP (see formula and Figure 15). This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO output clock is divided by the output prescaler (K = PLLODIV+1) to generate the master clock signal f MC. Therefore, the number of VCO cycles can be represented as K × N, where N is the number of consecutive f MC cycles (TCM). |
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