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SAK-XC161CJ-16F40F Datasheet(PDF) 10 Page - Infineon Technologies AG |
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SAK-XC161CJ-16F40F Datasheet(HTML) 10 Page - Infineon Technologies AG |
10 / 87 page XC161-16 Derivatives General Device Information Data Sheet 8 V2.3, 2006-03 2.2 Pin Configuration and Definition The pins of the XC161 are described in detail in Table 2, including all their alternate functions. Figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. E*) and C*) mark pins to be used as alternate external interrupt inputs, C*) marks pins that can have CAN/SDLM interface lines assigned to them. Figure 2 Pin Configuration (top view) MCP05390 TDO TMS P3.12/BHE/WRH/E*) P3.13/SCLK0/E*) P3.15/CLKOUT/FO V DDI P5.5/AN5 P5.4/AN4 P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 P9.5/SCL2/CC21IO P9.4/SDA2/CC20IO P9.3/SCL1/CC19IO/C*) P9.2/SDA1/CC18IO/C*) P9.1/SCL0/CC17IO/C*) P9.0/SDA0/CC16IO/C*) P7.7/CC31IO/C*) P7.6/CC30IO/C*) P7.5/CC29IO/C*) P7.4/CC28IO/C*) P6.7/BREQ/CC7IO P6.6/HLDA/CC6IO P6.5/HOLD/CC5IO P6.4/CS4/CC4IO P6.3/CS3/CC3IO P6.2/CS2/CC2IO P6.1/CS1/CC1IO P6.0/CS0/CC0IO NMI P20.12/RSTOUT N.C. N.C. V DDP V SSP V DDP VSSP V DDP V SSP V SSP V SSP P4.0/A16 V SSI P4.1/A17 P4.2/A18 P4.3/A19 P4.4/A20/C*) P4.5/A21/C*) P4.6/A22/C*) P4.7/A23/C*) V DDP V SSP P20.0/RD P20.1/WR/WRL P20.2/READY P20.4/ALE P20.5/EA P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 V DDP V SSP P0H.0/AD8 P0H.1/AD9 N.C. N.C. XC161 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
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