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COIC5130A Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers

Part No. COIC5130A
Description  Programmable Reed-Solomon Error Correction Encoder and Decoder
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Maker  ETC1 [List of Unclassifed Manufacturers]

COIC5130A Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers

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COic5130A Specifications
Co Optic
These properties must be initialized before normal operation can begin. There are two distinct phases of the initialization process. In phase
one, the values of P, STATEN and SHORT1 and SHORT2 are initialized. In phase two, the first message block through the device is used to
set the valuesof N, K and R.
The phase one sequence consists of at least 4 clock cycles in which RESET is held LOW followed by at least 2 clock cycles during which
is held HIGH. RESET must then remain HIGH for all subsequent operations or else an unwanted initialization sequence will ensue.
The desired values of STATEN and P4 - P0 must be maintained during the first phase of initialization. The desired value of SHORT1 and
must be maintained during all the phases of operation of the device. DATAEN must be held LOW during the entire six clock
sequence or unintended processing of spurious messages may occur.
Decoder Initialization Control Sequence Timing
The rising edge of DATAEN at the end of the phase one initialization sequence marks the beginning of the first message block, which is the
beginning of phase two of the initialization process. DATAEN has the role of initializing the parameters of N, K and R. DATAEN has a dif-
ferent function on all subsequent blocks until an initialization sequence is begun once again. As the first message block passes through the
device, DATAEN is held HIGH for K clock cycles and then LOW for R clock cycles. DATAEN going high again marks the first byte of the sec-
ond block and implies the end of the phase two initialization sequence. DATAEN has thus defined R, K and N for all subsequent blocks until
another initialization sequence is performed.
Decoder Message Input Timing
K Data Bytes
R Parity Bytes
At least 4 clock cycles
At least 2 clock cycles

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