CY7C4245-35ASC datasheet(10/25 Pages) CYPRESS

Part #	CY7C4245-35ASC

Description	64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C4425/4205/4215

CY7C4225/4235/4245

10

Notes:

19. PAE offset – n. Number of data words into FIFO already = n.

20. PAE offset – n.

21. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the

rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.

22. If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.

Switching Waveforms (continued)

tENH

Programmable Almost Empty Flag Timing

WCLK

PAE]

REN

RCLK

tCLKH

tPAE

tENS

n+1 WORDS

IN FIFO

tCLKL

tENS

tPAE

n WORDS IN FIFO

42X5–13

[19]

WEN

Note

tENH

WCLK

PAE

RCLK

tCLKH

tENS

tCLKL

tENS

tPAEsynch

N + 1 WORDS

INFIFO

42X5–14

tENH

tENS

tENH

tENS

tPAEsynch

REN

WEN

WEN2

tSKEW3

Note

Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)

[21]

22

20

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