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CY7C4235-15JC Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C4235-15JC
Description  64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C4235-15JC Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C4425/4205/4215
CY7C4225/4235/4245
3
Selection Guide
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Maximum Frequency (MHz)
100
66.7
40
28.6
Maximum Access Time (ns)
8
10
15
20
Minimum Cycle Time (ns)
10
15
25
35
Minimum Data or Enable Set-Up (ns)
3
4
6
7
Minimum Data or Enable Hold (ns)
0.5
1
1
2
Maximum Flag Delay (ns)
8
10
15
20
Operating Current (ICC2)
(mA) @ freq=20MHz
Commercial
45
45
45
45
Industrial
50
50
50
50
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
Density
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
Packages
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
Pin Definitions
Signal Name
Description
I/O
Function
D0–17
Data Inputs
I
Data inputs for an 18-bit bus
Q0–17
Data Outputs
O
Data outputs for an 18-bit bus
WEN
Write Enable
I
Enables the WCLK input
REN
Read Enable
I
Enables the RCLK input
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied
to VCC; it is synchronized to RCLK when VCC/SMODE is tied to VSS.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to
VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD
Load
I
When LD is LOW, D0 - 17 (O0 - 17) are written (read) into (from) the programma-
ble-flag-offset register.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to VSS; all other
devices will have FL tied to VCC. In standard mode of width expansion, FL is tied
to VSS on all devices.
Not Cascaded - Tied to VSS. Retransmit function is also available in standalone
mode by strobing RT.
WXI
Write Expansion
Input
I
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to VSS.


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