5 / 12 page
DA9122.002
7 September, 2001
5 (12)
x Load Regulation
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Load Regulation LDO_A
0 mA < IOUT < 135 mA
0 mA < IOUT < 100 mA
22
22
50
30
mV
Load Regulation LDO_B
0 mA < IOUT < 70 mA
21
25
mV
Load Regulation LDO_C
0 mA < IOUT < 50 mA
13
22
mV
x Line Regulation
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Line Regulation for all LDOs
IOUT = IMAX ,VIN from 5.3 V to 3.1 V
0.40
1.2
mV
x PSRR
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
PSRR for all LDOs
IOUT = Max IOUT
VIN = 3.6 V
f = 1 kHz
f = 10 kHz
47
75
63
dB
x Noise and Crosstalk
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Noise Voltage for all LDOs
VNO
100 Hz < f < 100 kHz
25
30
µVrms
x Dynamic Parameters
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Start-up Delay (from enabling
LDO_A to 90% * VOUT(NOM) ,
other LDOs at ON state)
(Note 2)
VENA from < 0.3 V to > 2.0 V,
VENBC > 2.0 V, IOUT = Max IOUT,
COUTA = 1
µF
25
µs
Overshoot
VENA from < 0.3 V to > 2.0 V,
VENBC > 2.0 V, IOUT = Max IOUT,
COUTA = 1
µF
1%
Settling Time
(from 90% * VOUT(NOM)A to max
±0.1% fluctuation)
VENA from < 0.3 V to > 2.0 V,
VENBC > 2.0 V, IOUT = Max IOUT,
COUTA = 1
µF, w/o C
BYPASS
200
µs
Note 2: When all regulators are disabled the start-up delay is a function of a bypass capacitor. Typically 0.5 ms for 10 nF capacitor.
TRL
VOUT
50%
start-up delay
90%
overshoot
settling time
Figure 1. Definitions of
start-up delay, overshoot
and settling time.
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