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HN58X2508I Datasheet(PDF) 17 Page - Renesas Technology Corp

Part No. HN58X2508I
Description  Electrically Erasable and Programmable Read Only Memory
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HN58X2508I Datasheet(HTML) 17 Page - Renesas Technology Corp

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HN58X2508I/HN58X2516I
Rev.2.00, Aug.19.2004, page 17 of 27
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect
(
W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allows the device to
be put in the Hardware Protected mode (When the Status Register Write Disable (SRWD) bit is set to 1, and
write protect (
W) signal is driven low). In this mode, the non-volatile bits of the Status Register (SRWD,
BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Write Status Register (WRSR):
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before
it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch(WEL).
The instruction sequence is shown in the following figure. The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip select (
S)
must be driven high after the rising edge of serial clock (C) that latches in the eighth bit of the data byte, and
before the next rising edge of serial clock (C). Otherwise, the Write Status Register (WRSR) instruction is
not executed. As soon as chip select (
S) is driven high, the self-timed Write Status Register cycle (whose
duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during
the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, Write
Enable Latch(WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the
values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as
defined in the Status Register Format table.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write
Disable (SRWD) bit in accordance with the write protect (
W) signal. The Status Register Write Disable
(SRWD) bit and write protect (
W) signal allows the device to be put in the Hardware Protected Mode (HPM).
The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is
entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at
their current values just before the start of the execution of the Write Status Register (WRSR) instruction.
The new, updated values take effect at the moment of completion of the execution of Write Status Register
(WRSR) instruction.


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