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CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 3 of 40
TXRATE
Character-Rate Clock
Bit-Rate Clock
HM L
TXCLK
8
TXCT[1:0]
TXD[7:0]
TXOP
TXPER
2
SCSEL
12
12
12
10
OUT1+
OUT1–
OUT2+
OUT2–
TXLB
Character-Rate Clock
SPDSEL
TXRST
TXMODE[1:0]
PARCTL
REFCLK+
REFCLK–
Transmit PLL
Clock Multiplier
Transmit
Mode
TXCLKO+
TXCLKO–
2
Logic Block Diagram
BISTLE
OELE
= Internal Signal
BIST Enable
Latch
Output
Enable
4
2
Latch
TXCKSEL
IN1+
IN1–
IN2+
IN2–
INSEL
TXLB
Character-Rate Clock
Clock &
Data
Recovery
PLL
LPEN
LFI
8
RXST[2:0]
RXD[7:0]
RXOP
3
Receive
Signal
Monitor
RXCLK+
RXCLK–
÷2
FRAMCHAR
RFMODE
RFEN
RXMODE
SDASEL
JTAG
Boundary
Scan
Controller
TDO
TMS
TCLK
TDI
Clock
Select
RXCKSEL
TRSTZ
DECMODE
RX PLL Enable
Latch
RXLE
BOE[1:0]
RXRATE
RXCLKC+
Delay