CY7C1381B
CY7C1383B
Document #: 38-05196 Rev. **
Page 6 of 31
Pin Definitions
Name
I/O
Description
A0
A1
A
Input-
Synchronous
Address inputs used to select one of the address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,
and CE3 are sampled active. A[1:0] feed the two-bit counter.
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable input, active LOW. When asserted LOW on the rising
edge of CLK, a global Write is conducted (ALL bytes are written, regardless
of the values on BWa,b,c,d and BWE).
BWE
Input-
Synchronous
Byte Write Enable input, active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte Write.
CLK
Input-Clock
Clock input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE1
Input-
Synchronous
Chip Enable 1 input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is
ignored if CE1 is HIGH.
CE2
Input-
Synchronous
Chip Enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device (TQFP only).
CE3
Input-
Synchronous
Chip Enable 3 input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device (TQFP only) .
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the first clock of a Read cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance input signal, sampled on the rising edge of CLK. When asserted,
it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK.
When asserted LOW, A is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK.
When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
MODE
Input-
Static
Selects burst order. When tied to GND selects linear burst sequence. When
tied to VDDQ or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
ZZ
Input-
Asynchronous
ZZ “sleep” input. This active HIGH input places the device in a
non-time-critical “sleep” condition with data integrity preserved.
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
I/O-
Synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A[X]during the previous clock
rise of the Read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQa–DQd and
DPa–DPd are placed in a three-state condition. DQ a,b,c and d are eight-bits
wide. DP a,b,c and d are one-bit wide.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK (BGA only).
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA
only).
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