CY7C1372BV25
CY7C1370BV25
Document #: 38-05252 Rev. **
Page 6 of 26
Introduction
Functional Overview
The CY7C1370BV25 and CY7C1372BV25 are synchronous-
pipelined Burst NoBL
SRAMs designed specifically to
eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 3.0 ns (200-MHz device).
Accesses can be initiated by asserting Chip Enable (CE1, CE2,
CE3 on the TQFP, CE1 on the BGA) active at the rising edge
of the clock. If Clock Enable (CEN) is active LOW and ADV/LD
is asserted LOW, the address presented to the device will be
latched. The access can either be a Read or Write operation,
depending on the status of the Write Enable (WE). BWS[d:a]
can be used to conduct byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed Write
circuitry.
Synchronous Chip Enable (CE1, CE2, CE3 on TQFP, CE1 on
BGA) and an asynchronous Output Enable (OE) simplify
depth
expansion.
All
operations
(Reads,
Writes,
and
Deselects) are pipelined. ADV/LD should be driven LOW once
the device has been deselected in order to load a new address
for the next operation.
Single Read Accesses
A Read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) chip
enable asserted active, (3) the Write Enable input signal WE
is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
Address Register and presented to the memory core and
control logic. The control logic determines that a Read access
is in progress and allows the requested data to propagate to
the input of the output register. At the rising edge of the next
clock the requested data is allowed to propagate through the
output register and onto the data bus within 3.0 ns (200-MHz
device) provided OE is active LOW. After the first clock of the
Read access the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. During the second
clock, a subsequent operation (Read/Write/Deselect) can be
initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will three-state following the next
clock rise.
Burst Read Accesses
The CY7C1370BV25/72BV25 have an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to Ax is loaded into
the Address Register. The Write signals are latched into the
Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DPa,b,c,d for CY7C1370BV25 and DQa,b/DPa,b for
CY7C1372BV25). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DP
(DQa,b,c,d/DPa,b,c,d for CY7C1370BV25 and DQa,b/DPa,b for
CY7C1372BV25) (or a subset for byte Write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the Write is complete.
The data written during the Write operation is controlled by
BWS (BWSa,b,c,d for CY7C1370BV25 and BWSa,b for
CY7C1372BV25)
signals.
The
CY7C1370BV25
and
CY7C1372BV25 provides byte Write capability that is
described in the Write Cycle Description table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK
(BGA only).
TCK
JTAG serial
clock
Serial clock to the JTAG circuit (BGA Only).
32M
64M
128M
–
No connects. Reserved for address expansion. Pins are not internally connected
NC
–
No connects. Pins are not internally connected.
DNU
–
Do not use pins.
Pin Definitions
Pin Name
I/O Type
Pin Description
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