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74ALVCH162245 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74ALVCH162245
Description  16-bit bus transceiver with direction pin and 30ohm termination resistor 3-State
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ALVCH162245 Datasheet(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74ALVCH162245
16-bit bus transceiver with direction pin and
30
Ω termination resistor (3-State)
2
1998 Jun 29
853-2085 19638
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple V
CC and ground pins for minimum noise
and ground bounce
Direct interface with TTL levels
Bus hold on all data inputs
Integrated 30Ω termination resistor
DESCRIPTION
The 74ALVCH162245 is a 16-bit transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
The 74ALVCH162245 features two output enable (nOE) inputs for
easy cascading and two send/receive (nDIR) inputs for direction
control. nOE controls the outputs so that the buses are effectively
isolated. This device can be used as two 8-bit transceivers or one
16-bit transceiver.
The 74ALVCH162245 is designed with 30
Ω series resistors in both
HIGH and LOW output states.
The 74ALVCH162245 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
GND
VCC1
GND
GND
VCC1
2A5
2A4
VCC2
2A3
2A2
GND
2A1
2A0
1A7
1A6
GND
1A5
1A4
VCC2
1A3
1A2
GND
1A1
1A0
1OE
21
22
23
24
25
26
27
28
GND
2DIR
2OE
2A7
2A6
GND
SW00198
1DIR
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An to Bn; Bn to An
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
2.4
ns
CI
Input capacitance
4.0
pF
CI/O
Input/output capacitance
8.0
pF
C
Power dissipation capacitance per buffer
V = GND to VCC1
Outputs enabled
27
pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
Outputs disabled
4
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
48-Pin Plastic SSOP Type III
–40
°C to +85°C
74ALVCH162245 DL
ACH162245 DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ALVCH162245 DGG
ACH162245 DGG
SOT362-1


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