512K x 36/1M x 18 Pipelined DCD SRAM
CY7C1386B
CY7C1387B
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05195 Rev. **
Revised December 3, 2001
86B
Features
• Fast clock speed: 200, 167, 150, 133 MHz
• Provide high-performance 3-1-1-1 access rate
•Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns
• Optimal for depth expansion
• 3.3V (–5% / +10%) power supply
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Double-cycle deselect
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down available using ZZ mode or CE
deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
• Automatic power down available using ZZ mode or CE
deselect
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The
CY7C1386B
and
CY7C1387B
SRAMs
integrate
524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, data
inputs, address-pipelining Chip Enables (CEs), burst control
inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). DQa,b,c,d and DPa,b,c,d apply to
CY7C1386B and DQa,b and DPa,b apply to CY7C1387B. a, b,
c, and d each are 8 bits wide in the case of DQ and 1 bit wide
in the case of DP.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycles. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DQPa. BWb controls DQb and DQPb. BWc
controls DQc and DQPd. BWd controls DQd–DQd and DQPd.
BWa, BWb, BWc, and BWd can be active only with BWE LOW.
GW LOW causes all bytes to be written. Write pass-through
capability allows written data available at the output for the
immediately next Read cycle. This device also incorporates
pipelined enable circuit for easy depth expansion without
penalizing system performance.
The CY7C1386B and CY7C1387B are both double-cycle
deselect parts. All inputs and outputs of the CY7C1386B and
the CY7C1387B are JEDEC-standard JESD8-5-compatible.
Selection Guide
200 MHz
167 MHz
150 MHz
133 MHz
Unit
Maximum Access Time
3
3.4
3.8
4.2
ns
Maximum Operating Current
315
285
265
245
mA
Maximum CMOS Standby Current
20
20
20
20
mA
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