Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1361A-100AJI Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1361A-100AJI
Description  256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
Download  26 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1361A-100AJI Datasheet(HTML) 8 Page - Cypress Semiconductor

Back Button CY7C1361A-100AJI Datasheet HTML 4Page - Cypress Semiconductor CY7C1361A-100AJI Datasheet HTML 5Page - Cypress Semiconductor CY7C1361A-100AJI Datasheet HTML 6Page - Cypress Semiconductor CY7C1361A-100AJI Datasheet HTML 7Page - Cypress Semiconductor CY7C1361A-100AJI Datasheet HTML 8Page - Cypress Semiconductor CY7C1361A-100AJI Datasheet HTML 9Page - Cypress Semiconductor CY7C1361A-100AJI Datasheet HTML 10Page - Cypress Semiconductor CY7C1361A-100AJI Datasheet HTML 11Page - Cypress Semiconductor CY7C1361A-100AJI Datasheet HTML 12Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 26 page
background image
CY7C1361A
CY7C1363A
Document #: 38-05259 Rev. *A
Page 8 of 26
Notes:
3.
X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, Write = L means [BWE + BWa*BWb]*GW equals LOW. Write = H means [BWE + BWa*BWb]*GW equals HIGH.
4.
BWa enables Write to DQa. BWb enables Write to DQb. BWc enables Write to DQc. BWd enables Write to DQd.
5.
All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
6.
Suspending burst generates wait cycle.l
7.
For a Write operation following a Read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
8.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9.
ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Burst Address Table (MODE = NC/VCC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Truth Table[3, 4, 5, 6, 7, 8, 9]
Operation
Address Used CE
CE2
CE2
ADSP
ADSC
ADV
Write
OE
CLK
DQ
Deselected Cycle, Power-down None
H
X
X
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
H
X
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
H
X
H
L
X
X
X
L-H
High-Z
Read Cycle, Begin Burst
External
L
L
H
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
L
H
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D


Similar Part No. - CY7C1361A-100AJI

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1361B CYPRESS-CY7C1361B Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361B-100AC CYPRESS-CY7C1361B-100AC Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361B-100AI CYPRESS-CY7C1361B-100AI Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361B-100AJC CYPRESS-CY7C1361B-100AJC Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361B-100AJI CYPRESS-CY7C1361B-100AJI Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
More results

Similar Description - CY7C1361A-100AJI

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1360A CYPRESS-CY7C1360A Datasheet
558Kb / 28P
   256K x 36/512K x 18 Synchronous Pipelined Burst SRAM
CY7C1355A CYPRESS-CY7C1355A Datasheet
563Kb / 28P
   256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
logo
GSI Technology
GS881E18 GSI-GS881E18 Datasheet
839Kb / 37P
   512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS88118AT GSI-GS88118AT Datasheet
876Kb / 36P
   512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS880E18AT GSI-GS880E18AT Datasheet
596Kb / 24P
   512K x 18, 256K x 32, 256K x 36 9Mb Synchronous Burst SRAMs
logo
Austin Semiconductor
AS5SS256K36 AUSTIN-AS5SS256K36 Datasheet
332Kb / 16P
   256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM
AS5SS256K36 AUSTIN-AS5SS256K36_05 Datasheet
397Kb / 16P
   256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM
logo
AMIC Technology
A67L93181 AMICC-A67L93181 Datasheet
246Kb / 18P
   512K X 18, 256K X 36 LVTTL, Flow-through ZeBL SRAM
logo
Cypress Semiconductor
CY7C1361B CYPRESS-CY7C1361B Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
logo
AMIC Technology
A67P93181 AMICC-A67P93181_15 Datasheet
251Kb / 18P
   512K X 18, 256K X 36 LVTTL, Flow-through ZeBL SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com