CY7C1360A
CY7C1362A
Document #: 38-05258 Rev. *A
Page 8 of 28
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 3.8 ns
(133-MHz device).
The CY7C1360A/CY7C1362A supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for 1360A and BWa,b
for 1362A) inputs. A Global Write Enable (GW) overrides all
byte Write inputs and writes data to all four bytes. All writes are
simplified with on-chip synchronous self-timed Write circuitry.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within preliminary ns (200-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always three-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will three-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
loaded into the address register and the address advancement
logic while being delivered to the RAM core. The Write signals
(GW, BWE, and BWx) and ADV inputs are ignored during this
first cycle.
ADSP triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the Write operation is controlled by BWE and BWx
signals. The CY7C1360A/CY7C1362A provides byte Write
capability that is described in the Write cycle description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BWa,b,c,d for CY7C1360A and BWa,b for
CY7C1362A) input will selectively write to only the desired
bytes. Bytes not selected during a byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1360A/CY7C1362A is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the Write inputs (GW, BWE,
and BWx) are asserted active to conduct a Write to the desired
byte(s). ADSC triggered Write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is
ignored during this cycle. If a global Write is conducted, the
data presented to the DQ[x:0] is written into the corresponding
address location in the RAM core. If a byte Write is conducted,
only the selected bytes are written. Bytes not selected during
a byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because the CY7C1360A/CY7C1362A is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ[x:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[x:0]
are automatically three-stated whenever a Write cycle is
detected, regardless of the state of OE.
Burst Sequences
The CY7C1360A/CY7C1362A provides a two-bit wraparound
counter, fed by A[1:0], that implements either an interleaved or
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel® Pentium® applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
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