CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
8
Notes:
3.
X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
4.
BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
5.
All inputs except OE must meet set up and hold times around the rising edge (LOW to HIGH) of CLK.
6.
Suspending burst generates wait cycle.
7.
For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
8.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9.
ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Burst Address Table (MODE = NC/VCC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Truth Table[3, 4, 5, 6, 7, 8, 9]
Operation
Address Used
CE
CE2 CE2 ADSP ADSC ADV WRITE OE
CLK
DQ
Deselected Cycle, Power
Down
None
H
X
X
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power
Down
None
L
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power
Down
None
L
H
X
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power
Down
None
L
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power
Down
None
L
H
X
H
L
X
X
X
L-H
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D
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