7 / 26 page  CY7C1361A CY7C1363A Document #: 38-05259 Rev. *A Page 7 of 26 2B 97 CE2 Input- Synchronous Chip Enable: This active HIGH input is used to enable the device. – (not available for PBGA) 92 (for A Version only) CE2 Input- Synchronous Chip Enable: This active LOW input is used to enable the device. Not available for BG and AJ package versions. 4F 86 OE Input Output Enable: This active LOW asynchronous input enables the data output drivers. 4G 83 ADV Input- Synchronous Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). 4A 84 ADSP Input- Synchronous Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. 4B 85 ADSC Input- Synchronous Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon Write control inputs. 3R 31 MODE Input- Static Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. An NC or HIGH on this pin selects Interleaved Burst. 7T 64 ZZ Input- Asynchronous Sleep: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 DQa DQb Input/ Output Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb. Input data must meet set-up and hold times around the rising edge of CLK. 2U 3U 4U 38 39 43 for BG and AJ version TMS TDI TCK Input IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not available for A package version. 5U 42 for BG and AJ version TDO Output IEEE 1149.1 Test Output: LVTTL-level output. Not available for A package version. 4C, 2J, 4J, 6J, 4R 15, 41,65, 91 V CC Supply Core Power Supply: +3.3V –5% and +10% 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 V SS Ground Ground: GND. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 4, 11, 20, 27, 54, 61, 70, 77 V CCQ I/O Power Supply Power Supply for the I/O circuitry 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 6U 1–3, 6, 7, 14, 16, 25, 28–30, 51–53, 56, 57, 66, 75, 78, 79, 80, 95, 96 38, 39, 42 for A Version NC – No Connect: These signals are not internally connected. User can leave it floating or connect it to V CC or VSS. 512K × 18 Pin Descriptions (continued) X18 PBGA Pins X18 QFP Pins Pin Name Type Pin Description |
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