8 / 31 page  CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Document #: 38-05161 Rev. *B Page 8 of 31 Notes: 2. L means logic LOW. H means logic HIGH. X means Don’t Care. 3. Multiple bytes may be selected during the same cycle. 4. BWc and BWd apply to 256K × 36 device only. 5. Upon completion of the Burst sequence, the counter wraps around to its initial state and continues counting. 4, 11, 20, 27, 54, 61, 70, 77 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VCCQ I/O Supply Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V I/O. +2.5V –0.125V and +0.4V for 2.5V I/O. 1-3, 6, 7, 25, 28-30, 51-53, 56, 57, 75, 78, 79, 84, 95, 96 4A, 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U NC – No Connect: These signals are not internally connected. It can be left floating or be connected to VCC or to GND. Pin Descriptions—512K × 18 (continued) 512K × 18 TQFP Pins 512K × 18 PBGA Pins Pin Name Type Pin Description Partial Truth Table for Read/Write[2] Function WEN BWa BWb BWc[4] BWd[4] Read H X X X X No Write L HH HH Write Byte a (DQa)[3] LL H H H Write Byte b (DQb)[3] LH LH H Write Byte c (DQc)[3] LH H L H Write Byte d (DQd}[3] LH H H L Write all bytes L L L L L Interleaved Burst Address Table (MODE = VCC or NC) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal)[5] A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A10 A...A11 A...A00 A...A01 A...A11 A...A10 A...A01 A...A00 Linear Burst Address Table (MODE = VSS) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal)[5] A...A00 A...A01 A...A10 A...A11 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A11 A...A00 A...A01 A...A10 |
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