CY7C1353B
PRELIMINARY
Document #: 38-05266 Rev. **
Page 4 of 15
Functional Overview
The CY7C1353B is a synchronous flow-through burst SRAM
designed
specifically
to
eliminate
wait
states
during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 7.5 ns (117-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access
can either be a read or write operation, depending on the sta-
tus of the Write Enable (WE). BWS[1:0] can be used to conduct
byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
86
OE
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence,
during the first clock when emerging from a deselected state, when the device has
been deselected.
87
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
23
−22,
19
−18,
13
−12, 9−8,
73
−72,
69
−68,
63
−62, 59−58
DQ[15:0]
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A[17:0] during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ[15:0] are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
24, 74
DP[1:0]
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to
DQ[15:0]. During write sequences, DP0 is controlled by BWS0 and DP1 is controlled
by BWS1.
31
Mode
Input
Strap pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floating MODE will default HIGH, to an inter-
leaved burst order.
15, 16, 41, 65,
91
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
4, 11, 20, 27,
54, 61, 70, 77
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
5, 10, 14, 17,
21, 26, 40, 55,
60, 64,
66
−67, 71,
76, 90
VSS
Ground
Ground for the device. Should be connected to ground of the system.
1
−3, 6−7, 25,
28
−30,51−53,
56
−57, 75,
78
−79, 95−96
NC
-
No Connects. These pins are not connected to the internal device.
83, 84
NC
-
No Connects. Reserved for address inputs for depth expansion. Pin 83 will be used
for 512K depth and pin 84 will be used for 1-Mb depth.
38, 39, 42, 43
DNU
-
Do Not Use Pins. These pins should be left floating or tied to VSS.
Pin Definitions (continued)
Pin Number
Name
I/O
Description
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