CY7C1338B
Document #: 38-05143 Rev. **
Page 3 of 18
Pin Descriptions
Name
I/O
Description
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is
captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is
captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
A[1:0]
Input-
Synchronous
A1, A0 Address Inputs. These inputs feed the on-chip burst counter as the LSBs as well as being
used to access a particular memory location in the memory array.
A[16:2]
Input-
Synchronous
Address Inputs used in conjunction with A[1:0] to select one of the 64K address locations. Sampled
at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active
LOW.
BW[3:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the
rising edge. BW0 controls DQ[7:0] and DP0, BW1 controls DQ[15:8] and DP1, BW2 controls DQ[23:16]
and DP2, and BW3 controls DQ[31:24] and DP3. See Write Cycle Descriptions table for further details.
ADV
Input-
Synchronous
Advance Input used to advance the on-chip address counter. When LOW the internal burst counter
is advanced in a burst sequence. The burst sequence is selected using the MODE input.
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
GW
Input-
Synchronous
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct
a global write, independent of the state of BWE and BW[3:0]. Global writes override byte writes.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. CE1 gates ADSP.
Pin Configurations (continued)
23
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
NC
DQc
DQd
DQc
DQd
AA
A
A
ADSP
VDDQ
CE2
A
DQc
VDDQ
DQc
VDDQ
VDDQ
VDDQ
DQd
DQd
NC
NC
VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VDD
TDO
TCK
TDI
TMS
NC
NC
NC
VDDQ
VDDQ
VDDQ
AA
A
A
NC
A
A
A
A
A
A
A0
A1
DQa
DQc
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
DQb
VDD
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
ADSC
NC
CE1
OE
ADV
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
MODE
NC
NC
BWb
BWc
NC
VDD
NC
BWa
NC
BWE
BWd
ZZ
CY7C1338B (128K x 32)
119-Ball BGA
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