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ADSP21062 Datasheet(PDF) 3 Page - Analog Devices |
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ADSP21062 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 48 page 
ADSP-21062/ADSP-21062L –3– REV. B including a 2 Mbit SRAM memory (4 Mbit on the ADSP-21060), host processor interface, DMA controller, serial ports and link port and parallel bus connectivity for glueless DSP multiprocessing. Figure 1 shows a block diagram of the ADSP-21062, illustrating the following architectural features: Computation Units (ALU, Multiplier and Shifter) with a Shared Data Register File Data Address Generators (DAG1, DAG2) Program Sequencer with Instruction Cache Interval Timer On-Chip SRAM External Port for Interfacing to Off-Chip Memory and Peripherals Host Port and Multiprocessor Interface DMA Controller Serial Ports and Link Ports JTAG Test Access Port Figure 2 shows a typical single-processor system. A multi- processing system is shown in Figure 3. Table I. ADSP-21062/ADSP-21062L Benchmarks (@ 40 MHz) 1024-Pt. Complex FFT 0.46 ms 18,221 cycles (Radix 4, with Digit Reverse) FIR Filter (per Tap) 25 ns 1 cycle IIR Filter (per Biquad) 100 ns 4 cycles Divide (y/x) 150 ns 6 cycles Inverse Square Root (1/ √x) 225 ns 9 cycles DMA Transfer Rate 240 Mbytes/s S GENERAL NOTE This data sheet represents production released specifications for the ADSP-21062 (5 V) and ADSP-21062L (3.3 V) processors, for both 33 MHz and 40 MHz speed grades. The product name “ADSP-21062” is used throughout this data sheet to represent all devices, except where expressly noted. GENERAL DESCRIPTION The ADSP-21062 SHARC—Super Harvard Architecture Computer—is a signal processing microcomputer that offers new capabilities and levels of performance. The ADSP-21062 SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-21062 builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual- ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus. Fabricated in a high speed, low power CMOS process, the ADSP-21062 has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle. Table I shows performance benchmarks for the ADSP-21062. The ADSP-21062 SHARC represents a new standard of inte- gration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features |
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