ii
6.19
CL .............................................................................................................................................. 10
6.20
M ................................................................................................................................................ 11
6.21
MID0~MID2................................................................................................................................ 11
6.22
SYNC ......................................................................................................................................... 11
6.23
MODE ........................................................................................................................................ 11
6.24
TEST_IN0~1 .............................................................................................................................. 11
6.25
TEST0~14.................................................................................................................................. 11
6.26
N/C............................................................................................................................................. 11
6.27
Dummy...................................................................................................................................... 11
7
FUNCTIONAL BLOCK DESCRIPTIONS ........................................................................................ 12
7.1
Command Decoder and Command Interface........................................................................ 12
7.2
MPU Parallel 6800-series Interface ........................................................................................ 12
7.3
MPU Parallel 8080-series Interface ........................................................................................ 12
7.4
MPU Serial 4-wire Interface.....................................................................................................13
7.5
MPU Serial 3-wire interface.....................................................................................................13
7.6
Graphic Display Data RAM (GDDRAM).................................................................................. 13
7.7
Oscillator Circuit ...................................................................................................................... 13
7.8
LCD Driving Voltage Generator and Regulator .................................................................... 14
7.9
169 Bit Latch ............................................................................................................................ 14
7.10
Level selector ........................................................................................................................... 14
7.11
HV Buffer Cell (Level Shifter)..................................................................................................14
7.12
Default Setting after Reset...................................................................................................... 15
7.13
LCD Panel Driving Waveform ................................................................................................. 16
COMMAND TABLE .................................................................................................................................... 20
7.14
Read Status Byte ..................................................................................................................... 25
7.15
Data Read / Write ..................................................................................................................... 25
8
COMMAND DESCRIPTIONS .......................................................................................................... 26
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