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74ALS109A Datasheet(PDF) 4 Page - NXP Semiconductors

Part No. 74ALS109A
Description  Dual J-K positive edge-triggered flip-flop with set and reset
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74ALS109A Datasheet(HTML) 4 Page - NXP Semiconductors

   
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Philips Semiconductors
Product specification
74ALS109A
Dual J-K positive edge triggered flip-flop
with set and reset
1991 Feb 08
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS1
MIN
TYP2
MAX
UNIT
VOH
High-level output voltage
VCC = ±10%,
VIL = MAX, VIH = MIN
IOH = –0.4mA
VCC – 2
V
VO
Low level output voltage
VCC = MIN, VIL = MAX,
IOL = 4mA
0.25
0.40
V
VOL
Low-level output voltage
CC
,
IL
,
VIH = MIN
IOL = 8mA
0.35
0.50
V
VIK
Input clamp voltage
VCC = MIN, II = IIK
–0.73
–1.5
V
I
Input current at maximum input
Jn, Kn, CPn
VCC = MAX V =7 0V
0.1
mA
II
voltage
SDn, RDn
VCC = MAX, VI = 7.0V
0.2
mA
I
High level input current
Jn, Kn, CPn
VCC = MAX V =2 7V
20
µA
IIH
High–level input current
SDn, RDn
VCC = MAX, VI = 2.7V
40
µA
I
Low level input current
Jn, Kn, CPn
VCC = MAX V =0 4V
–0.2
mA
IIL
Low–level input current
SDn, RDn
VCC = MAX, VI = 0.4V
–0.4
mA
IO
Output current3
VCC = MAX, VO = 2.25V
–30
–112
mA
ICC
Supply current (total)4
VCC = MAX
3.0
4.0
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, IOS.
4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs High in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
UNIT
MIN
MAX
fMAX
Maximum clock frequency
Waveform 1
80
MHz
tPLH
tPHL
Propagation delay
CPn to Qn or Qn
Waveform 1
3.0
3.0
14.0
14.0
ns
tPLH
tPHL
Propagation delay
SDn or RD to Qn or Qn
Waveform 2, 3
1.0
3.0
8.0
10.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
UNIT
MIN
MAX
tsu (H)
tsu (L)
Setup time, High or Low
Jn, Kn to CPn
Waveform 1
6.0
6.0
ns
th (H)
th (L)
Hold time, High or Low
Jn, Kn to CPn
Waveform 1
0.0
0.0
ns
tw (H)
tw (L)
CPn Pulse width
High or Low
Waveform 1
6.0
6.0
ns
tw (L)
SDn or RDn Pulse width
Low
Waveform 2, 3
6.0
ns
trec
Recovery time, SDn or RDn to CPn
Waveform 2, 3
6.0
ns


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