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74AHCU04 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74AHCU04
Description  Hex inverter
Download  16 Pages
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74AHCU04 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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1999 Sep 27
2
Philips Semiconductors
Product specification
Hex inverter
74AHCU04
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger
actions
• Inputs accepts voltages higher than
VCC
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHCU04 is high-speed Si-gate
CMOS devices and is pin compatible
with low power Schottky TTL
(LSTTL). It is specified in compliance
with JEDEC standard No. 7A.
The 74AHCU04 is a general purpose
hex inverter. Each of the six inverters
is a single stage.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
INPUT nA
OUTPUT nY
LH
HL
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
PINNING
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay
nA to nY
CL =15pF;
VCC =5V
1.5
ns
CI
input capacitance
VI =VCC or GND
3.0
pF
CO
output capacitance
4.0
pF
CPD
power dissipation
capacitance
CL =50pF;
f = 1 MHz;
notes 1 and 2
9.1
pF
PIN
SYMBOL
DESCRIPTION
1, 3, 5, 9, 11 and 13
1A to 6A
data inputs
2, 4, 6, 8, 10 and 12
1Y to 6Y
data outputs
7
GND
ground (0 V)
14
VCC
DC supply voltage


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