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74AHC574 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74AHC574
Description  Octal D-type flip-flop; positive edge-trigger; 3-state
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74AHC574 Datasheet(HTML) 2 Page - NXP Semiconductors

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1999 Jun 16
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC574;
74AHCT574
FEATURES
• 3-state non-inverting outputs for
bus oriented applications
• 8-bit positive, edge-triggered
register
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
• Independent register and 3-state
buffer operation
• Common 3-state output enable
input
• Output capability; bus driver
• ICC category: MSI
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT574 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard no. 7A.
The 74AHC/AHCT574 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation
of the OE input does not affect the state of the flip-flops.
The ‘574’ is functionally identical to the ‘564’, but has non-inverting outputs.
The ‘574’ is functionally identical to the ‘374’, but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay
CL = 15 pF; VCC = 5 V
4.4
4.4
ns
CP to Qn
fmax
maximum clock frequency
CL = 15 pF; VCC = 5 V
130
130
MHz
CI
input capacitance
VI =VCC or GND
4.0
4.0
pF
CO
output capacitance
4.0
4.0
pF
CPD
power dissipation
capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
10
12
pF


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