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SI9124 Datasheet(PDF) 5 Page - Vishay Siliconix |
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SI9124 Datasheet(HTML) 5 Page - Vishay Siliconix |
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Si9124 Vishay Siliconix New Product Document Number: 72099 S-03638—Rev. B, 20-Mar-03 www.vishay.com 5 SPECIFICATIONSa Limits - 40 to 85 _C Test Conditions Unless Specified CS1 = CS2 = 0 V, fNOM = 500 kHz, VIN = 48 V VINDET = 4.8 V; 10 V v VCC v 13.2 V, VCC2 = VCC Parameter Unit Maxb Typc Minb Test Conditions Unless Specified CS1 = CS2 = 0 V, fNOM = 500 kHz, VIN = 48 V VINDET = 4.8 V; 10 V v VCC v 13.2 V, VCC2 = VCC Symbol Output A Primary Driver Output High Voltage VOH Sourcing 10 mA VCC2 - 0.3 V Output Low Voltage VOL Sinking 10 mA PGND2 + 0.3 V VCC2 Current ICC5 0.1 1.55 1.1 mA Peak Output Source ISOURCE VCC2 = 12 V, PGND2 = 0 V - 1.0 - 0.75 A Peak Output Sink ISINK VCC2 12 V, PGND2 0 V 0.75 1.0 A Rise Time tr TA = 25_C COUTA = 3 nF VCC = 12 V 20 80% 18 28 ns Fall Time tf TA = 25_C, COUTA = 3 nF, VCC = 12 V, 20 - 80% 22 28 ns Output B Primary Driver Output High Voltage VOH Sourcing 10 mA VCC - 0.3 V Output Low Voltage VOL Sinking 10 mA 0.3 V Peak Output Source ISOURCE VCC = 12 V PGND = 0 V - 1.0 - 0.75 A Peak Output Sink ISINK VCC = 12 V, PGND = 0 V 0.75 1.0 A Rise Time tr TA = 25_C COUTB = 3 nF VCC = 12 V 20 80% 19 28 ns Fall Time tf TA = 25_C, COUTB = 3 nF, VCC = 12 V, 20 - 80% 24 28 ns Secondary_Synchronous Driver Output High Voltage VOH Sourcing 10 mA VCC - 0.4 V Output Low Voltage VOL Sinking 10 mA 0.4 V Leading Edge Delays td1 TA = 25_C VCC = 12 V LX = 48 V See Figure 3 80 110 Leading Edge Delays td3 TA = 25_C, VCC = 12 V, LX = 48 V, See Figure 3 80 110 ns Trailing Edge Delays td2 COUTA = COUTB = 3nF CSEC SYNC = 0 3 nF 80 110 ns Trailing Edge Delays td4 COUTA = COUTB = 3nF, CSEC_SYNC = 0.3 nF 80 110 Peak Output Source ISOURCE VCC = 12 V - 100 mA Peak Output Sink ISINK VCC = 12 V 100 mA Rise Time tr TA = 25_C CSEC SYNC = 0 3 nF VCC = 12 V 20 80% 16 28 ns Fall Time tf TA = 25_C, CSEC_SYNC = 0.3 nF, VCC = 12 V, 20 - 80% 17 28 ns Voltage Mode Error Amplifier td1A Input to A-side switch off t200 ns Error Amplifier td1A td2B Input to B-side switch off t200 ns Current Mode Current Amplifier td3A Input to A-side switch off t200 ns Current Amplifier td3A td4B Input to B-side switch off t200 ns Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum ( - 40 _ to 85_C). c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VCC = 12 V unless otherwise noted. d. VUVLO tracks VREG1 by a diode drop. e. Measured on OUTA or OUTB outputs. f. Note total supply current drawn is ICC3 plus ICC5. |
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