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74AHC126 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74AHC126
Description  Quad buffer/line driver; 3-state
Download  16 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74AHC126 Datasheet(HTML) 2 Page - NXP Semiconductors

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1999 Sep 29
2
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger
actions
• Inputs accepts voltages higher than
VCC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT126 are
high-speed Si-gate CMOS devices
and are pin compatible with low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT126 are four
non-inverting buffer/line drivers with
3-state outputs. The 3-state outputs
(nY) are controlled by the output
enable input (nOE) A LOW at nOE
causes the outputs to assume a
HIGH-impedance OFF state.
The ‘126’ is identical to the ‘125’ but
has active HIGH enable inputs.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF state.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
PINNING
INPUTS
OUTPUT
nOE
nA
nY
HL
L
HHH
LX
Z
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay
nA to nY
CL =15pF;
VCC =5V
3.3
3.0
ns
CI
input capacitance
VI =VCC or GND
3.0
3.0
pF
CO
output capacitance
4.0
4.0
pF
CPD
power dissipation
capacitance
CL =50pF;
f = 1 MHz;
notes 1 and 2
10
12
pF
PIN
SYMBOL
DESCRIPTION
1, 4, 10 and 13
1OE to 4OE
output enable inputs (active HIGH)
2, 5, 9 and 12
1A to 4A
data inputs
3, 6, 8 and 11
1Y to 4Y
data outputs
7
GND
ground (0 V)
14
VCC
DC supply voltage


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