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The Western Design Center, Inc.
W65C21S Data Sheet
AC TIMING CHARACTERISTICS
14 MHz @ 5V
ymbol
Min
Max
Unit
tCYC
70
-
Para
ulse Width
and F
TIMING
Pa
s Set-Up Ti
ral Data Setu
meter
S
PHI2 Cycle
ns
PHI2 P
tC
35
-
ns
PHI2 Rise
all Time
-
5
ns
t t
rc fc
READ
14 MHz @ 5V
rameter
S
ol
Min
Max
Unit
ymb
Addres
me
R
10
-
ns
tAC
Address Hold Time
R
0
-
ns
tCA
Periphe
p Time
10
-
ns
tPCR
Data Bus Delay Time
-
20
ns
tCDR
Data Bus Hold Time
HR
5
-
ns
t
WRITE TIMING
14 MHz @ 5V
bol
nit
AW
ns
W
Data Bus Hold Time
tHW
5
-
ns
Peripheral Data Delay Time
tCP
-
20
ns
W
PERIPHERAL INTERFACE TI
G
14 MHz @ 5V
MIN
bol
Unit
S1
ns
PHI2 High to CB2 Low Delay
tCB
-
70
2
ns
tRS1
ns
CA1, CA1, CB1, and CB2
Input Rise and Fall Time
tr, f
-
10
t
ns
I
3
ns
Parameter
Sym
Min
Max
U
Address Set-Up Time
tACW
10
-
ns
Address Hold Time
tC
0
-
Data Bus Set-Up Time
tDC
10
-
ns
Parameter
Sym
Min
Max
PHI2 Low to CA2 Low Delay
tCA2
-
20
ns
PHI2 Low to CA2 High Delay
tR
-
20
CA1 Active to CA2 High Delay
tRS2
-
25
ns
Peripheral Data Valid to CB2 Low
Delay
tDC
5
-
ns
PHI2 High to CB2 High Delay
-
20
CB1 Active to CB2 High Delay
tRS2
-
25
ns
Interrupt Input Pulse Width
PW
-
70
ns
Interrupt Response Time
tRS
-
20
Interrupt Clear Delay
tIR
-
25
ns
The Western Design Center
W65C21S
6
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