21:3 LVDS Transmitter
CS5820
BLOCK DIAGRAM
GENERAL DESCRIPTION
Myson-Century Technology
FEATURES
USA:
4020 Moorpark Avenue Suite
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
Sales@myson.com.tw
www.myson.com.tw
Rev.1.6 October 2001
page 1 of 12
Myson-Century Technology, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
CS5820 receives three sets of 7-bit data in CMOS
logic level and convert them into three low-voltage
differential signaling (LVDS) serial channels. The 7-
bit input data is referenced to the CKIN signal. The
RF pin selects either rising or falling edge trigger of
CKIN. Parallel to serial conversion is performed by a
7X internal generated clock reference using on-chip
PLL using CKIN. A copy of CKIN but phase-locked to
the
output
serial
streams,
CLKOUT,
is
also
converted to the fourth LVDS channel. CS5820
offers a reliable communication media using LVDS
signaling and provides low EMI dealing with wide,
high-speed TTL interfaces.
This is especially attractive for interfaces between
GUI controller and display systems such as LCD
panels for SVGA/XGA/SXGA applications.
• Three 7-bit serial and one clock LVDS channels.
• Compatible with ANSI TIA/EIA-644 LVDS stan-
dard.
• Wide CKIN ranges from 31MHz to 68MHz.
• Fully integrated on-chip PLL that provides 7X
CKIN serial shift clock.
• Pin selectable for rising or falling edge trigger.
• Support power-down mode.
• 5V/3.3V tolerant data input.
• Single 3.3V supply operation.
• CMOS low power consumption.
• Functional compatible with DS90C363 and
SN75LVDS84.
• Available in 48-pin TSSOP package.
PARALLEL-IN SERIAL-OUT
D0-D6
7-Bit SHIFT REGISTER
SHIFT/LOAD_N
CLK
DIN
PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
SHIFT/LOAD_N
DIN
PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
SHIFT/LOAD_N
DIN
CLK
CLK
PHASE LOCK LOOP
R/F
CLK
7xCLK
SHIFT/LOAD_N
CONTROL LOGIC
D7-D13
D14-D20
RF
CKIN
SHTDN
EN
Y0P
Y0N
EN
Y1P
Y1N
EN
Y2P
Y2N
EN
CKOP
CKON
CS5820
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