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GS8322V18GE-200I Datasheet(PDF) 10 Page - GSI Technology |
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GS8322V18GE-200I Datasheet(HTML) 10 Page - GSI Technology |
10 / 42 page Preliminary GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C) Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.04 4/2005 10/42 © 2003, GSI Technology GS8322V18/36 119-Bump BGA Pin Description Symbol Type Description A0, A1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I Clock Input Signal; active high BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low E1 I Chip Enable; active low G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock VDD I Core power supply VSS I I/O and Core Ground VSS I I/O and Core Ground VDDQ I Output driver power supply |
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