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GS8324Z72C-200I Datasheet(PDF) 6 Page - GSI Technology |
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GS8324Z72C-200I Datasheet(HTML) 6 Page - GSI Technology |
6 / 46 page ![]() Rev: 1.00 10/2001 6/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C) P6 ZZ I Sleep Mode control; active high L6 FT I Flow Through or Pipeline mode; active low T6 LBO I Linear Burst Order mode; active low G6, J6 MCH I Must Connect High N6 MCH I Must Connect High (x72 and x36 versions) H6, J6, K6, M6 MCL Must Connect Low A8, N6 MCL Must Connect Low (x18 version) B6 W I Write Enable; active low T7 PE I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) F6 ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) W3 TMS I Scan Test Mode Select W4 TDI I Scan Test Data In W8 TDO O Scan Test Data Out W9 TCK I Scan Test Clock A4, N6 VDD I Core power supply (x18 version) E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5, R6, R7 VDD I Core power supply D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7, H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3, P4, P5, P7, P8, P9, T3, T9 VSS I I/O and Core Ground E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9, L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9 VDDQ I Output driver power supply GS8324Z18/36/72 209-Bump BGA Pin Description Pin Location Symbol Type Description |
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