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GS8342R08E Datasheet(PDF) 14 Page - GSI Technology |
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GS8342R08E Datasheet(HTML) 14 Page - GSI Technology |
14 / 37 page Preliminary GS8342R08/09/18/36E-333/300/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.02 8/2005 14/37 © 2003, GSI Technology B4 State Diagram Power-Up NOP Load New Address DDR Read DDR Write LOAD READ WRITE LOAD LOAD LOAD LOAD Notes: 1. The internal burst address counter is a 4-bit linear counter (i.e., when first address is A0, next internal burst address is A0+1). 2. “READ” refers to read active status with R/W = High, “WRITE” refers to write inactive status with R/W = Low. 3. “LOAD” refers to read new address active status with LD = Low, “LOAD” refers to read new address inactive status with LD = High. LOAD Increment Read Address Increment Write Address Always Always READ WRITE |
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