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XRT75R12D Datasheet(PDF) 3 Page - Exar Corporation |
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XRT75R12D Datasheet(HTML) 3 Page - Exar Corporation |
3 / 131 page ![]() XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER PRELIMINARY REV. P1.0.1 I TABLE OF CONTENTS GENERAL DESCRIPTION.............................................................................................................. 1 APPLICATIONS ............................................................................................................................................................... 1 FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R12D.................................................................................................................................. 1 ORDERING INFORMATION .................................................................................................................... 1 FEATURES..................................................................................................................................................................... 2 TRANSMIT INTERFACE CHARACTERISTICS ....................................................................................................................... 2 RECEIVE INTERFACE CHARACTERISTICS ......................................................................................................................... 2 PIN DESCRIPTIONS (BY FUNCTION) ........................................................................................... 3 SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS....................................................................................... 3 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS ....................................................................................... 6 RECEIVE LINE SIDE PINS ............................................................................................................................................... 8 CLOCK INTERFACE......................................................................................................................................................... 9 GENERAL CONTROL PINS ............................................................................................................................................ 10 POWER SUPPLY PINS .................................................................................................................................................. 12 GROUND PINS ............................................................................................................................................................. 13 FUNCTIONAL DESCRIPTION ...................................................................................................... 18 1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) ....................................... 18 1.1 NETWORK ARCHITECTURE ......................................................................................................................... 18 FIGURE 2. NETWORK REDUNDANCY ARCHITECTURE ............................................................................................................................. 18 2.0 CLOCK SYNTHESIZER ....................................................................................................................... 19 2.1 CLOCK DISTRIBUTION ................................................................................................................................. 19 FIGURE 4. CLOCK DISTRIBUTION CONGIFURED IN E3 MODE WITHOUT USING SFM ................................................................................ 19 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR ............................................ 19 3.0 THE RECEIVER SECTION .................................................................................................................. 20 FIGURE 5. RECEIVE PATH BLOCK DIAGRAM .......................................................................................................................................... 20 3.1 RECEIVE LINE INTERFACE .......................................................................................................................... 20 FIGURE 6. RECEIVE LINE INTERFACECONNECTION................................................................................................................................. 20 3.2 ADAPTIVE GAIN CONTROL (AGC) .............................................................................................................. 21 3.3 RECEIVE EQUALIZER ................................................................................................................................... 21 FIGURE 7. ACG/EQUALIZER BLCOK DIAGRAM ....................................................................................................................................... 21 3.3.1 RECOMMENDATIONS FOR EQUALIZER SETTINGS .............................................................................................. 21 3.4 CLOCK AND DATA RECOVERY ................................................................................................................... 21 3.4.1 DATA/CLOCK RECOVERY MODE ............................................................................................................................ 21 3.4.2 TRAINING MODE........................................................................................................................................................ 21 3.5 LOS (LOSS OF SIGNAL) DETECTOR ........................................................................................................... 22 3.5.1 DS3/STS-1 LOS CONDITION ..................................................................................................................................... 22 3.5.2 DISABLING ALOS/DLOS DETECTION ..................................................................................................................... 22 TABLE 2: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) .......................................................................................................................................................... 22 3.5.3 E3 LOS CONDITION:.................................................................................................................................................. 23 FIGURE 8. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 .................................................................................................. 23 FIGURE 9. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775................................................................................................... 23 3.5.4 INTERFERENCE TOLERANCE.................................................................................................................................. 24 FIGURE 10. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1 ...................................................................................................... 24 FIGURE 11. INTERFERENCE MARGIN TEST SET UP FOR E3. ................................................................................................................... 24 TABLE 3: INTERFERENCE MARGIN TEST RESULTS ................................................................................................................................. 25 3.5.5 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 26 3.6 B3ZS/HDB3 DECODER .................................................................................................................................. 26 FIGURE 12. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING ........................................................................................................ 26 4.0 THE TRANSMITTER SECTION ........................................................................................................... 27 FIGURE 13. TRANSMIT PATH BLOCK DIAGRAM ...................................................................................................................................... 27 4.1 TRANSMIT DIGITAL INPUT INTERFACE ..................................................................................................... 27 FIGURE 14. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75R12D (DUAL-RAIL DATA)............................................ 27 FIGURE 15. TRANSMITTER TERMINAL INPUT TIMING............................................................................................................................... 28 FIGURE 16. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED) .................................................................. 28 4.2 TRANSMIT CLOCK ........................................................................................................................................ 29 4.3 B3ZS/HDB3 ENCODER .................................................................................................................................. 29 4.3.1 B3ZS ENCODING ....................................................................................................................................................... 29 4.3.2 HDB3 ENCODING....................................................................................................................................................... 29 |