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XRT75R06DIB Datasheet(PDF) 29 Page - Exar Corporation |
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XRT75R06DIB Datasheet(HTML) 29 Page - Exar Corporation |
29 / 105 page áç áç áç áç XRT75R06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 24 3.5.5 Muting the Recovered Data with LOS condition: When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to “1”. NOTE: When the LOS condition is cleared, the recovered data is output on RxPOS_n and RxNEG_n pins. 3.6 B3ZS/HDB3 Decoder The decoder block takes the output from the clock and data recovery block and decodes the B3ZS (for DS3 or STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data stream. Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV_n output pins to indicate line code violation. FIGURE 13. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING SYMBOL PARAMETER MIN TYP MAX UNITS RxClk Duty Cycle 45 50 55 % RxClk Frequency E3 DS-3 STS-1 34.368 44.736 51.84 MHz MHz MHz tRRX RxClk rise time (10% o 90%) 2 4 ns tFRX RxClk falling time (10% to 90%) 2 4 ns tCO RxClk to RPOS/RNEG delay time 4 ns tLCVO RxClk to rising edge of LCV output delay 2.5 ns RxClk t RRX t FRX RPOS or RNEG LCV t LCVO t CO |
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