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XRT75R06D Datasheet(PDF) 5 Page - Exar Corporation

Part No. XRT75R06D
Description  SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
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XRT75R06D Datasheet(HTML) 5 Page - Exar Corporation

 
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XRT75R06D
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
II
Figure 15. Typical interface between terminal equipment and the XRT75R06D (dual-rail data) ................... 25
Figure 16. Transmitter Terminal Input Timing ................................................................................................ 26
Figure 17. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 26
4.2 TRANSMIT CLOCK ............................................................................................................................................ 27
4.3 B3ZS/HDB3 ENCODER ................................................................................................................................... 27
4.3.1 B3ZS Encoding .................................................................................................................................. 27
4.3.2 HDB3 Encoding .................................................................................................................................. 27
Figure 18. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 27
Figure 19. B3ZS Encoding Format ................................................................................................................. 27
4.4 TRANSMIT PULSE SHAPER ............................................................................................................................... 28
Figure 21. Transmit Pulse Shape Test Circuit ................................................................................................ 28
4.4.1 Guidelines for using Transmit Build Out Circuit ............................................................................. 28
Figure 20. HDB3 Encoding Format ................................................................................................................ 28
4.5 E3 LINE SIDE PARAMETERS .............................................................................................................................. 29
Figure 22. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ................................................... 29
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS .......................... 30
Figure 23. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ......... 31
TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................ 31
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) . 32
Figure 24. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................ 32
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) .... 33
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................... 33
4.6 TRANSMIT DRIVE MONITOR .............................................................................................................................. 34
4.7 TRANSMITTER SECTION ON/OFF ....................................................................................................................... 34
Figure 25. Transmit Driver Monitor set-up. ..................................................................................................... 34
5.0 Jitter .................................................................................................................................................. 35
5.1 JITTER TOLERANCE .......................................................................................................................................... 35
5.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 35
Figure 26. Jitter Tolerance Measurements ..................................................................................................... 35
5.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 36
Figure 27. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 36
Figure 28. Input Jitter Tolerance for E3 ......................................................................................................... 36
5.2 JITTER TRANSFER ............................................................................................................................................ 37
5.3 JITTER ATTENUATOR ........................................................................................................................................ 37
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ....................................... 37
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................. 37
5.3.1 Jitter Generation ................................................................................................................................ 38
TABLE 10: JITTER TRANSFER PASS MASKS ....................................................................................................... 38
Figure 29. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 38
6.0 Diagnostic Features ......................................................................................................................... 39
6.1 PRBS GENERATOR AND DETECTOR ................................................................................................................. 39
Figure 30. PRBS MODE ................................................................................................................................. 39
6.2 LOOPBACKS ................................................................................................................................................ 40
6.2.1 ANALOG LOOPBACK ........................................................................................................................ 40
Figure 31. Analog Loopback ........................................................................................................................... 40
6.2.2 DIGITAL LOOPBACK ......................................................................................................................... 41
6.2.3 REMOTE LOOPBACK ........................................................................................................................ 41
Figure 32. Digital Loopback ............................................................................................................................ 41
Figure 33. Remote Loopback ......................................................................................................................... 41
6.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 42
Figure 34. Transmit All Ones (TAOS) ............................................................................................................. 42
7.0 Microprocessor interface Block ..................................................................................................... 43
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ...................................................................... 43
Figure 35. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 43
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ........................................................................................ 44
TABLE 12: XRT75R06D MICROPROCESSOR INTERFACE SIGNALS ...................................................................... 44


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