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XRT75R03 Datasheet(PDF) 5 Page - Exar Corporation

Part No. XRT75R03
Description  THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
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XRT75R03 Datasheet(HTML) 5 Page - Exar Corporation

 
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XRT75R03
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.7
II
6.0 THE RECEIVER SECTION: ................................................................................................................. 43
6.1 AGC/EQUALIZER: .......................................................................................................................................... 43
6.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 44
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 44
FIGURE 19. INTERFERENCE MARGIN TEST SET UP FOR E3. ............................................................................................................ 45
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 45
6.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 45
6.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 46
6.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 46
6.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 46
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3
AND
STS-1 APPLICATIONS)............................................................................................................................................. 46
DISABLING ALOS/DLOS DETECTION: .......................................................................................................... 46
6.4.2 E3 LOS CONDITION:.................................................................................................................................................. 46
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.......................................................................................... 47
FIGURE 21. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ......................................................................................... 47
6.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 48
7.0 JITTER: ................................................................................................................................................ 48
7.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 48
FIGURE 22. JITTER TOLERANCE MEASUREMENTS ........................................................................................................................... 48
7.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 48
FIGURE 23. INPUT JITTER TOLERANCE FOR DS3/STS-1................................................................................................................ 49
7.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 49
FIGURE 24. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 49
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) .................................................................. 50
7.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 50
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................................................ 50
7.3 JITTER ATTENUATOR: ................................................................................................................................. 50
TABLE 13: JITTER TRANSFER PASS MASKS .................................................................................................................................... 51
FIGURE 25. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 51
7.3.1 JITTER GENERATION: .............................................................................................................................................. 51
8.0 SERIAL HOST INTERFACE: ............................................................................................................... 51
TABLE 14: FUNCTIONS OF SHARED PINS ......................................................................................................................................... 52
TABLE 15: XRT75R03 REGISTER MAP - QUICK LOOK .................................................................................................................... 53
Legend: ..................................................................................................................................................................... 56
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75R03 3-CHANNEL DS3/E3/STS-1 LIU IC 56
TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC56
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................ 58
TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS ................................................................................................. 58
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................... 58
TABLE 18: APS/REDUNDANCY CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) ............................................................... 58
TABLE 19: BLOCK LEVEL INTERRUPT ENABLE REGISTER - CR32 (ADDRESS LOCATION = 0X20)....................................................... 61
TABLE 20: BLOCK LEVEL INTERRUPT STATUS REGISTER - CR33 (ADDRESS LOCATION = 0X21)....................................................... 62
TABLE 21: DEVICE/PART NUMBER REGISTER - CR62 (ADDRESS LOCATION = 0X3E) ....................................................................... 63
TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F)..................................................................... 64
THE PER-CHANNEL REGISTERS ........................................................................................................... 64
TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC64
REGISTER DESCRIPTION - PER CHANNEL REGISTERS .................................................................... 66
TABLE 24: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X01 .............................................. 66
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02 .............................................. 68
TABLE 26: ALARM STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X03............................................................................. 70
TABLE 27: TRANSMIT CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X04 ..................................................................... 75
TABLE 28: RECEIVE CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X05 ....................................................................... 78
TABLE 29: CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ...................................................................... 80
TABLE 30: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ..................................................... 83
9.0 DIAGNOSTIC FEATURES: ................................................................................................................. 84
9.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 84
FIGURE 26. PRBS MODE ............................................................................................................................................................. 84
9.2 LOOPBACKS: ................................................................................................................................................ 84
9.2.1 ANALOG LOOPBACK:............................................................................................................................................... 84
FIGURE 27. ANALOG LOOPBACK..................................................................................................................................................... 85
9.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 86
FIGURE 28. DIGITAL LOOPBACK...................................................................................................................................................... 86


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